X86 INSTRUCTIONS::::::DATA TRANSFER INSTRUCTION::::2- DATA SWAP

Exchange : Syntax : xchg src, dest #GAS Syntax xchg dest, src #Intel syntax The xchg instruction swaps the src operand with the dest operand. It's like doing three move operations: from dest to a temporary (another register), then from src to dest, then from the temporary to src, except that no register needs to be reserved for temporary storage. If one of the operands is a memory address, then the operation has an implicit LOCK prefix, that is, the exchange operation is atomic. This can have a large performance penalty. It's also worth noting that the common NOP (no op) instruction, 0x90, is the opcode for xchgl %eax, %eax. Operands src Register Memory dest Register Memory However, only one operand can be in memory: the other must be a register. Modified flags No FLAGS are modified by this instruction Example : .data value: .long 2 .text .global _start _start: movl $54, %ebx xorl %eax, %eax xchgl value, %ebx # %ebx is now 2 # value is now 54 xchgw %ax, value # Value is now 0 # %eax is now 54 xchgb %al, %bl # %ebx is now 54 # %eax is now 2 xchgw value(%eax), %ax # value is now 0x00020000 = 131072 # %eax is now 0 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80 Compare and exchange : Syntax : cmpxchg arg2, arg1 #GAS Syntax cmpxchg arg1, arg2 #Intel syntax The cmpxchg instruction has two implicit operands AL/AX/EAX(depending on the size of arg1) and ZF(zero) flag. The instruction compares arg1 to AL/AX/EAX and if they are equal sets arg1 to arg2 and sets the zero flag, otherwise it sets AL/AX/EAX to arg1 and clears the zero flag. Unlike xchg there is not an implicit lock prefix and if the instruction is required to be atomic then lock must be prefixed. Operands arg1 Register Memory arg2 Register Modified flags The ZF flag is modified by this instruction In order to assemble, link and run the program we need to do the following: $ nasm -felf32 -g cmpxchgSpinLock.asm $ gcc -o cmpxchgSpinLock cmpxchgSpinLock.o -lpthread $ ./cmpxchgSpinLock