GENERAL PURPOSE REGISTERS IN A MICROPROCESSOR

64-bit x86 adds 8 more general-purpose registers, named R8, R9, R10 and so on up to R15. It also introduces a new naming convention that must be used for these new registers and can also be used for the old ones (except that AH, CH, DH and BH have no equivalents). In the new convention : R0 is RAX. R1 is RCX. R2 is RDX. R3 is RBX. R4 is RSP. R5 is RBP. R6 is RSI. R7 is RDI. R8,R9,R10,R11,R12,R13,R14,R15 are the new registers and have no other names. R0D~R15D are the lowermost 32 bits of each register. For example, R0D is EAX. R0W~R15W are the lowermost 16 bits of each register. For example, R0W is AX. R0L~R15L are the lowermost 8 bits of each register. For example, R0L is AL. As well, 64-bit x86 includes SSE2, so each 64-bit x86 CPU has at least 8 registers (named XMM0~XMM7) that are 128 bits wide, but only accessible through SSE instructions. They cannot be used for quadruple-precision (128-bit) floating-point arithmetic, but they can each hold 2 double-precision or 4 single-precision floating-point values for a SIMD parallel instruction. They can also be operated on as 128-bit integers or vectors of shorter integers. If the processor supports AVX, as newer Intel and AMD desktop CPUs do, then each of these registers is actually the lower half of a 256-bit register (named YMM0~YMM7), the whole of which can be accessed with AVX instructions for further parallelization.