ASSEMBLY PROGRAM::: SUBTRACTION OF TWO 8 - BIT NO.

.model small .data num1 db 22h num2 db 11h .code .startup main: mov ax,@data mov ds,ax mov al,num1 sub al,num2 .exit end

ASSEMBLY PROGRAM:: ADD TWO 8 BIT NO.

.model small .data num1 db 22h num2 db 11h .code .startup main: mov ax,@data mov ds,ax mov al,num1 add al,num2 .exit end

X86 INSTRUCTIONS:::X86 INTERRUPT

Interrupts are special routines that are defined on a per-system basis. This means that the interrupts on one system might be different from the interrupts on another system. Therefore, it is usually a bad idea to rely heavily on interrupts when you are writing code that needs to be portable. What is an Interrupt? In modern operating systems, the programmer often doesn't need to use interrupts. In Windows, for example, the programmer conducts business with the Win32 API. However, these API calls interface with the kernel, and the kernel will often trigger interrupts to perform different tasks. In older operating systems (specifically DOS), the programmer didn't have an API to use, and so they had to do all their work through interrupts. Interrupt Instruction This instruction issues the specified interrupt. For instance: Syntax 1 : int arg Calls interrupt 10 (0x0A (hex) = 10 (decimal)). Syntax 2 : int 0x0A Types of Interrupts There are 3 types of interrupts: Hardware Interrupts, Software Interrupts and Exceptions. Hardware Interrupts Hardware interrupts are triggered by hardware devices. For instance, when you type on your keyboard, the keyboard triggers a hardware interrupt. The processor stops what it is doing, and executes the code that handles keyboard input (typically reading the key you pressed into a buffer in memory). Hardware interrupts are typically asynchronous - their occurrence is unrelated to the instructions being executed at the time they are raised. Software Interrupts There are also a series of software interrupts that are usually used to transfer control to a function in the operating system kernel. Software interrupts are triggered by the instruction int. For example, the instruction "int 14h" triggers interrupt 0x14. The processor then stops the current program, and jumps to the code to handle interrupt 14. When interrupt handling is complete, the processor returns flow to the original program. Exceptions Exceptions are caused by exceptional conditions in the code which is executing, for example an attempt to divide by zero or access a protected memory area. The processor will detect this problem, and transfer control to a handler to service the exception. This handler may re-execute the offending code after changing some value (for example, the zero dividend), or if this cannot be done, the program causing the exception may be terminated.

X86 INSTRUCTIONS:::OTHER INSTRUCTION:::SYSTEM INSTRUCTIONS

These instructions were added with the Pentium II. Syntax 1 : sysenter This instruction causes the processor to enter protected system mode (supervisor mode or "kernel mode"). Syntax 2 : sysexit This instruction causes the processor to leave protected system mode, and enter user mode.

X86 INSTRUCTIONS:::OTHER INSTRUCTION:::I/O INSTRUCTIONS

The IN instruction almost always has the operands AX and DX (or EAX and EDX) associated with it. DX (src) frequently holds the port address to read, and AX (dest) receives the data from the port. In Protected Mode operating systems, the IN instruction is frequently locked, and normal users can't use it in their programs. Syntax 1 : in src, dest #GAS Syntax in dest, src #Intel syntax The OUT instruction is very similar to the IN instruction. OUT outputs data from a given register (src) to a given output port (dest). In protected mode, the OUT instruction is frequently locked so normal users can't use it. Syntax 2 : out src, dest #GAS Syntax out dest, src #Intel syntax

X86 INSTRUCTIONS:::OTHER INSTRUCTION:::FLAGS INSTRUCTIONS

While the flags register is used to report on results of executed instructions (overflow, carry, etc.), it also contains flags that affect the operation of the processor. These flags are set and cleared with special instructions. Interrupt Flag The IF flag tells a processor if it should accept hardware interrupts. It should be kept set under normal execution. In fact, in protected mode, neither of these instructions can be executed by user-level programs. Syntax 1 : sti Sets the interrupt flag. If set, the processor can accept interrupts from peripheral hardware. Syntax 2 : cli Clears the interrupt flag. Hardware interrupts cannot interrupt execution. Programs can still generate interrupts, called software interrupts, and change the flow of execution. Non-maskable interrupts (NMI) cannot be blocked using this instruction. Direction Flag The DF flag tells the processor which way to read data when using string instructions. That is, whether to decrement or increment the esi and edi registers after a movs instruction. Syntax 1 : std Sets the direction flag. Registers will decrement, reading backwards. Syntax 2 : cld Clears the direction flag. Registers will increment, reading forwards. Carry Flag The CF flag is often modified after arithmetic instructions, but it can be set or cleared manually as well. Syntax 1 : stc Sets the carry flag. Syntax 2 : clc Clears the carry flag. Syntax 3 : cmc Complements (inverts) the carry flag. Other Syntax 1 : sahf Stores the content of AH register into the lower byte of the flag register. Syntax 2 : lahf Loads the AH register with the contents of the lower byte of the flag register.

X86 INSTRUCTIONS:::OTHER INSTRUCTION:::STACK INSTRUCTIONS

Push instruction decrements the stack pointer and stores the data specified as the argument into the location pointed to by the stack pointer. Syntax 1 : push arg Pop instruction loads the data stored in the location pointed to by the stack pointer into the argument specified and then increments the stack pointer. Syntax 2 : pop arg Example : mov eax, 5 mov ebx, 6 push eax #The stack is now: [5] push ebx #The stack is now: [6] [5] /*The topmost item (which is 6) is now stored in eax. The stack is now: [5]*/ pop eax #ebx is now equal to 5. The stack is now empty. pop ebx Pushf instruction decrements the stack pointer and then loads the location pointed to by the stack pointer with the contents of the flag register. Syntax 1 : pushf Popf instruction loads the flag register with the contents of the memory location pointed to by the stack pointer and then increments the contents of the stack pointer. Syntax 2 : popf Pusha instruction pushes all the general purpose registers onto the stack in the following order: AX, CX, DX, BX, SP, BP, SI, DI. The value of SP pushed is the value before the instruction is executed. It is useful for saving state before an operation that could potential change these registers. Syntax 1 : pusha Popa instruction pops all the general purpose registers off the stack in the reverse order of PUSHA. That is, DI, SI, BP, SP, BX, DX, CX, AX. Used to restore state after a call to PUSHA. Syntax 2 : popa Pushad instruction works similarly to pusha, but pushes the 32-bit general purpose registers onto the stack instead of their 16-bit counterparts. Syntax 1 : pushad Popad instruction works similarly to popa, but pops the 32-bit general purpose registers off of the stack instead of their 16-bit counterparts. Syntax 2 : popad

X86 INSTRUCTIONS:::SHIFT AND ROTATE:::FOR A ROTATE

Rotate Instructions In a rotate instruction, the bits that slide off the end of the register are fed back into the spaces. Rotate dest to the right by src bits. Syntax 1 : ror src, dest #GAS Syntax ror dest, src #Intel syntax Rotate dest to the left by src bits. Syntax 2 : rol src, dest #GAS Syntax rol dest, src #Intel syntax Rotate With Carry Instructions Like with shifts, the rotate can use the carry bit as the "extra" bit that it shifts through. Rotate dest to the right by src bits with carry. Syntax 1 : rcr src, dest #GAS Syntax rcr dest, src #Intel syntax Rotate dest to the left by src bits with carry. Syntax 2 : rcl src, dest #GAS Syntax rcl dest, src #Intel syntax Number of arguments Unless stated, these instructions can take either one or two arguments. If only one is supplied, it is assumed to be a register or memory location and the number of bits to shift/rotate is one (this may be dependent on the assembler in use, however). shrl $1, %eax is equivalent to shrl %eax (GAS syntax).

X86 INSTRUCTIONS:::SHIFT AND ROTATE:::FOR A SHIFT

Logical Shift Instructions In a logical shift instruction (also referred to as unsigned shift), the bits that slide off the end disappear (except for the last, which goes into the carry flag), and the spaces are always filled with zeros. Logical shifts are best used with unsigned numbers. Syntax 1 : shr src, dest #GAS Syntax shr dest, src #Intel syntax Logical shift dest to the right by src bits. Syntax 2 : shl src, dest #GAS Syntax shl dest, src #Intel syntax Logical shift dest to the left by src bits. Example (GAS Syntax) : /*ax=1111.1111.0000.0000 (0xff00, unsigned 65280, signed -256)*/ movw $ff00,%ax /*ax=0001.1111.1110.0000 (0x1fe0, signed and unsigned 8160)*/ shrw $3,%ax /*(logical shifting unsigned numbers right by 3 is like integer division by 8)*/ /*ax=0011.1111.1100.0000 (0x3fc0, signed and unsigned 16320)*/ shlw $1,%ax /*(logical shifting unsigned numbers left by 1 is like multiplication by 2)*/ Arithmetic Shift Instructions In an arithmetic shift (also referred to as signed shift), like a logical shift, the bits that slide off the end disappear (except for the last, which goes into the carry flag). But in an arithmetic shift, the spaces are filled in such a way to preserve the sign of the number being slid. For this reason, arithmetic shifts are better suited for signed numbers in two's complement format. Syntax 1 : sar src, dest #GAS Syntax sar dest, src #Intel syntax Arithmetic shift dest to the right by src bits. Spaces are filled with sign bit (to maintain sign of original value), which is the original highest bit. Syntax 2 : sal src, dest #GAS Syntax sal dest, src #Intel syntax Arithmetic shift dest to the left by src bits. The bottom bits do not affect the sign, so the bottom bits are filled with zeros. This instruction is synonymous with SHL. Example (GAS Syntax) : /*ax=1111.1111.0000.0000 (0xff00, unsigned 65280, signed -256)*/ movw $ff00,%ax /*ax=1111.1100.0000.0000 (0xfc00, unsigned 64512, signed -1024)*/ salw $2,%ax /*(arithmetic shifting left by 2 is like multiplication by 4 for negative numbers, but has an impact on positives with most significant bit set (i.e. set bits shifted out))*/ /*ax=1111.1111.1110.0000 (0xffe0, unsigned 65504, signed -32)*/ sarw $5,%ax /*(arithmetic shifting right by 5 is like integer division by 32 for negative numbers)*/ Extended Shift Instructions The names of the double precision shift operations are somewhat misleading, hence they are listed as extended shift instructions on this page. They are available for use with 16- and 32-bit data entities (registers/memory locations). The src operand is always a register, the dest operand can be a register or memory location, the cnt operand is an immediate byte value or the CL register. In 64-bit mode it is possible to address 64-bit data as well. The operation performed by shld is to shift the most significant cnt bits out of dest, but instead of filling up the least significant bits with zeros, they are filled with the most significant cnt bits of src. Syntax 1 : shld cnt, src, dest #GAS Syntax shld dest, src, cnt #Intel syntax Likewise, the shrd operation shifts the least significant cnt bits out of dest, and fills up the most significant cnt bits with the least significant bits of the src operand. Syntax 2 : shrd cnt, src, dest #GAS Syntax shrd dest, src, cnt #Intel syntax Intel's nomenclature is misleading, in that the shift does not operate on double the basic operand size (i.e. specifying 32-bit operands doesn't make it a 64-bit shift): the src operand always remains unchanged. Also, Intel's manual states that the results are undefined when cnt is greater than the operand size, but at least for 32- and 64-bit data sizes it has been observed that shift operations are performed by (cnt mod n), with n being the data size. Example (GAS Syntax) : # ax=0000.0000.0000.0000 (0x0000) xorw %ax,%ax # ax=1111.1111.1111.1111 (0xffff) notw %ax # bx=0101.0101.0000.0000 movw $0x5500,%bx # bx=1111.0101.0101.0000 (0xf550), ax is still 0xffff shrdw $4,%ax,%bx # ax=1111.1111.1111.0101 (0xfff5), bx is still 0xf550 shldw $8,%bx,%ax Example : (decimal numbers are used instead of binary number to explain the concept) : # ax = 1234 5678 # bx = 8765 4321 shrd $3, %ax, %bx # ax = 1234 5678 bx = 6788 7654 # ax = 1234 5678 # bx = 8765 4321 shld $3, %ax, %bx # bx = 5432 1123 ax = 1234 5678

X86 INSTRUCTIONS::: LOGICAL INSTRUCTIONS

The instructions are of bit-wise logical instructions. Bit-wise AND Syntax : and src, dest #GAS Syntax and dest, src #Intel syntax Performs a bit-wise AND of the two operands, and stores the result in dest. Example : movl $0x1, %edx movl $0x0, %ecx andl %edx, %ecx ; here ecx would be 0 because 1 AND 0 = 0 Bit-wise OR Syntax : or src, dest #GAS Syntax or dest, src #Intel syntax Performs a bit-wise OR of the two operands, and stores the result in dest. Example : movl $0x1, %edx movl $0x0, %ecx orl %edx, %ecx ; here ecx would be 1 because 1 OR 0 = 1 Bit-wise XOR Syntax : xor src, dest #GAS Syntax xor dest, src #Intel syntax Performs a bit-wise XOR of the two operands, and stores the result in dest. Example : movl $0x1, %edx movl $0x0, %ecx xorl %edx, %ecx ; here ecx would be 1 because 1 XOR 0 = 1 Bit-wise Inversion Syntax : not arg Performs a bit-wise inversion of arg. Example : movl $0x1, %edx notl %edx /*here edx would be 0xFFFFFFFE because a bitwise NOT 0x00000001 = 0xFFFFFFFE*/

X86 INSTRUCTIONS::: CARRY AIRTHMETIC INSTRUCTION

Syntax 1 : adc src, dest #GAS Syntax adc dest, src #Intel syntax Add with carry. Adds src + carry flag to dest, storing result in dest. Usually follows a normal add instruction to deal with values twice as large as the size of the register. In the following example, source contains a 64-bit number which will be added to destination. Example : mov eax, [source] ; read low 32 bits mov edx, [source+4] ; read high 32 bits add [destination], eax ; add low 32 bits adc [destination+4], edx ; add high 32 bits, plus carry Syntax 2 : sbb src, dest #GAS Syntax sbb dest, src #Intel syntax Subtract with borrow. Subtracts src + carry flag from dest, storing result in dest. Usually follows a normal sub instruction to deal with values twice as large as the size of the register.

X86 INSTRUCTIONS:::AIRTHMETIC INSTRUCTION

Arithmetic instructions take two operands: a destination and a source. The destination must be a register or a memory location. The source may be either a memory location, a register, or a constant value. Atleast one of the two must be a register, because operations may not use a memory location as both a source and a destination. Syntax 1 : add src, dest #GAS Syntax add dest, src #Intel syntax This adds src to dest. If you are using the MASM syntax, then the result is stored in the first argument, if you are using the GAS syntax, it is stored in the second argument. Syntax 2 : sub src, dest #GAS Syntax sub dest, src #Intel syntax Like ADD, only it subtracts source from destination instead. In C: dest -= src; Syntax 3 : mul arg This multiplies "arg" by the value of corresponding byte-length in the AX register. operand size 1 byte 2 bytes 4 bytes other operand AL AX EAX higher part of result stored in: AH DX EDX lower part of result stored in: AL AX EAX In the second case, the target is not EAX for backward compatibility with code written for older processors. Syntax 4 : imul arg As MUL, only signed. The IMUL instruction has the same format as MUL, but also accepts two other formats like so: Syntax 5 : imul src, dest #GAS Syntax imul dest, src #Intel syntax This multiplies src by dest. If you are using the NASM syntax, then the result is stored in the first argument, if you are using the GAS syntax, it is stored in the second argument. Syntax 6 : imul aux, src, dest #GAS Syntax imul dest, src, aux #Intel syntax This multiplies src by aux and places it into dest. If you are using the NASM syntax, then the result is stored in the first argument, if you are using the GAS syntax, it is stored in the third argument. Syntax 7 : div arg This divides the value in the dividend register(s) by "arg", see table below. divisor size 1 byte 2 bytes 4 bytes dividend AX DX:AX EDX:EAX remainder stored in: AH DX EDX quotient stored in: AL AX EAX The colon (:) means concatenation. With divisor size 4, this means that EDX are the bits 32-63 and EAX are bits 0-31 of the input number (with lower bit numbers being less significant, in this example). As you typically have 32-bit input values for division, you often need to use CDQ to sign-extend EAX into EDX just before the division. If quotient does not fit into quotient register, arithmetic overflow interrupt occurs. All flags are in undefined state after the operation. Syntax 8 : idiv arg As DIV, only signed. Syntax 9 : neg arg Arithmetically negates the argument (i.e. two's complement negation).

X86 INSTRUCTIONS:::CONTROL FLOW:::JUMP INSTRUCTION:::OTHER CONTROL INSTRUCTION

Syntax 1 : hlt Halts the processor. Execution will be resumed after processing next hardware interrupt, unless IF is cleared. Syntax 2 : nop No operation. This instruction doesn't do anything, but wastes an instruction cycle in the processor. This instruction is often represented as an XCHG operation with the operands EAX and EAX. Syntax 3 : lock Asserts #LOCK prefix on next instruction. Syntax 4 : wait Waits for the FPU to finish its last calculation.

X86 INSTRUCTIONS:::CONTROL FLOW:::JUMP INSTRUCTION:::ENTER AND LEAVE

Syntax 1 : enter arg Creates a stack frame with the specified amount of space allocated on the stack. Syntax 2 : leave Destroys the current stack frame, and restores the previous frame. Using Intel syntax this is equivalent to: Syntax 3 : mov esp, ebp pop ebp This will set EBP and ESP to their respective value before the function prologue began therefore reversing any modification to the stack that took place during the prologue.

X86 INSTRUCTIONS:::CONTROL FLOW::: JUMP INSTRUCTIONS:::LOOP INSTRUCTION

Syntax : loop arg The loop instruction decrements ECX and jumps to the address specified by arg unless decrementing ECX caused its value to become zero. Example mov ecx, 5 start_loop: ; the code here would be executed 5 times loop start_loop loop does not set any flags. Syntax : loopx arg These loop instructions decrement ECX and jump to the address specified by arg if their condition is satisfied (that is, a specific flag is set), unless decrementing ECX caused its value to become zero. loope loop if equal loopne loop if not equal loopnz loop if not zero loopz loop if zero

X86 INSTRUCTIONS:::CONTROL FLOW:::JUMP INSTRUCTION::: FUNCTION CALLS

Syntax : call proc Pushes the address of the next opcode onto the top of the stack, and jumps to the specified location. This is used mostly for subroutines. Syntax : ret [val] Loads the next value on the stack into EIP, and then pops the specified number of bytes off the stack. If val is not supplied, the instruction will not pop any values off the stack after returning

X86 INSTRUCTIONS:::CONTROL FLOW:::: JUMP INSTRUCTIONS

The Jump Instructions allow the programmer to (indirectly) set the value of the EIP register. The location passed as the argument is usually a label. The first instruction executed after the jump is the instruction immediately following the label. All of the jump instructions, with the exception of jmp, are conditional jumps, meaning that program flow is diverted only if a condition is true. These instructions are often used after a comparison instruction, but since many other instructions set flags, this order is not required. Unconditional Jumps : Syntax : jmp loc Loads EIP with the specified address (i.e. the next instruction executed will be the one specified by jmp). Jump on Equality : Syntax : je loc ZF = 1 Loads EIP with the specified address, if operands of previous CMP instruction are equal. mov $5, ecx mov $5, edx cmp ecx, edx je equal ; if it did not jump to the label equal, then this means ecx and edx are not equal. equal: ; if it jumped here, then this means ecx and edx are equal Jump on Inequality : Syntax : jne loc ZF = 0 Loads EIP with the specified address, if operands of previous CMP instruction are not equal. Jump if Greater : Syntax 1 : jg loc ZF = 0 and SF = OF Loads EIP with the specified address, if first operand of previous CMP instruction is greater than the second (performs signed comparison). Syntax 2 : jge loc SF = OF Loads EIP with the specified address, if first operand of previous CMP instruction is greater than or equal to the second (performs signed comparison). Syntax 3 : ja loc CF = 0 and ZF = 0 Loads EIP with the specified address, if first operand of previous CMP instruction is greater than the second. ja is the same as jg, except that it performs an unsigned comparison. Syntax 4 : jae loc CF = 0 Loads EIP with the specified address, if first operand of previous CMP instruction is greater than or equal to the second. jae is the same as jge, except that it performs an unsigned comparison. Jump if Less : Syntax 1 : jl loc The criteria required for a JL is that SF <> OF, loads EIP with the specified address, if the criteria is meet. So either SF or OF can be set but not both in order to satisfy this criteria. If we take the SUB(which is basically what a CMP does) instruction as an example, we have: arg2 - arg1 With respect to SUB and CMP there are several cases that fulfill this criteria: arg2 < arg1 and the operation does not have overflow arg2 > arg1 and the operation has an overflow In case 1) SF will be set but not OF and in case 2) OF will be set but not SF since the overflow will reset the most significant bit to zero and thus preventing SF being set. The SF <> OF criteria avoids the cases where: arg2 > arg1 and the operation does not have overflow arg2 < arg1 and the operation has an overflow arg2 == arg1 In case 1) neither SF nor OF are set, in case 2) OF will be set and SF will be set since the overflow will reset the most significant bit to one and in case 3) neither SF nor OF will be set. The example code below runs the five cases outlined above and prints out whether SF and OF are equal or not: ; ; nasm -felf32 -g jlFlagsCheck.asm ; gcc -o jlFlagsCheck jlFlagsCheck.o ; global main extern printf section .data sfneofStr: db 'SF <> OF', 0xA, 0 sfeqofStr: db 'SF == OF', 0xA, 0 section .bss section .text main: ; ; Functions will follow the cdecl call convention ; ; ; arg2 < arg1 and no overflow ; mov eax, 1 cmp eax, 2 call checkSFNEOF ; ; arg2 < arg1 and overflow ; mov al, -2 cmp al, 127 call checkSFNEOF ; ; arg2 > arg1 and no overflow ; mov eax, 2 cmp eax, 1 call checkSFNEOF ; ; arg2 > arg1 and overflow ; mov al, 127 cmp al, -1 call checkSFNEOF ; ; arg2 == arg1 ; mov eax, 2 cmp eax, 2 call checkSFNEOF call exit ; ; Check if SF <> OF, which means the condition for jump less would be meet. ; checkSFNEOF: push ebp mov ebp, esp jl SFNEOF jmp SFEQOF SFNEOF: push dword sfneofStr call printf jmp checkSFNEOFDone SFEQOF: push dword sfeqofStr call printf checkSFNEOFDone: leave ret exit: ; ; Call exit(3) syscall ; void exit(int status) ; mov ebx, 0 ; Arg one: the status mov eax, 1 ; Syscall number: int 0x80 Output : SF <> OF SF <> OF SF == OF SF == OF SF == OF Syntax 2 : jb loc CF = 1 Loads EIP with the specified address, if first operand of previous CMP instruction is less than the second. jb is the same as jl, except that it performs an unsigned comparison. Syntax 3 : jbe loc CF = 1 or ZF = 1 Loads EIP with the specified address, if first operand of previous CMP instruction is less than or equal to the second. jbe is the same as jle, except that it performs an unsigned comparison. Jump on Overflow : Syntax 1 : jo loc OF = 1 Loads EIP with the specified address, if the overflow bit is set on a previous arithmetic expression. Syntax 2 : jno loc OF = 0 Loads EIP with the specified address, if the overflow bit is not set on a previous arithmetic expression. Jump on Zero : Syntax 1 : jz loc ZF = 1 Loads EIP with the specified address, if the zero bit is set from a previous arithmetic expression. jz is identical to je. Syntax 2 : jnz loc ZF = 0 Loads EIP with the specified address, if the zero bit is not set from a previous arithmetic expression. jnz is identical to jne. Jump on Sign : Syntax 1 : js loc SF = 1 Loads EIP with the specified address, if the sign bit is set from a previous arithmetic expression. Syntax 2 : jns loc SF = 0 Loads EIP with the specified address, if the sign bit is not set from a previous arithmetic expression.

X86 INSTRUCTIONS:::CONTROL FLOW::: comparison instruction

Performs a bit-wise logical AND on arg1 and arg2 the result of which we will refer to as Temp and sets the ZF(zero), SF(sign) and PF(parity) flags based on Temp. Temp is then discarded. Syntax test arg1, arg2 #GAS Syntax test arg2, arg1 #Intel syntax Operands arg1 Register Immediate arg2 AL/AX/EAX (only if arg1 is immediate) Register Memory Modified flags SF <- MostSignificantBit(Temp) If Temp == 0 ZF <- 1 else ZF <- 0 PF <- BitWiseXorNor(Temp[Max-1:0]) CF <- 0 OF <- 0 AF is undefined Performs a comparison operation between arg1 and arg2. The comparison is performed by a (signed) subtraction of arg2 from arg1, the results of which can be called Temp. Temp is then discarded. If arg2 is an immediate value it will be sign extended to the length of arg1. The EFLAGS register is set in the same manner as a sub instruction. Syntax cmp arg2, arg1 #GAS Syntax cmp arg1, arg2 #Intel syntax the GAS/AT&T syntax can be rather confusing, as for example cmp $0, %rax followed by jl branch will branch if %rax < 0 (and not the opposite as might be expected from the order of the operands). Operands arg1 AL/AX/EAX (only if arg2 is immediate) Register Memory arg2 Register Immediate Memory Modified flags SF <- MostSignificantBit(Temp) If Temp == 0 ZF <- 1 else ZF <- 0 PF <- BitWiseXorNor(Temp[Max-1:0]) CF, OF and AF<- 0

X86 INSTRUCTIONS:::CONTROL FLOW:::INTRODUCTION

Almost all programming languages have the ability to change the order in which statements are evaluated, and assembly is no exception. The instruction pointer (EIP) register contains the address of the next instruction to be executed. To change the flow of control, the programmer must be able to modify the value of EIP. This is where control flow functions come in. mov eip, label ; wrong jmp label ; right

DATA TRANSFER INSTRUCTION FOR 8086 MICROPROCESSOR

General purpose byte or word transfer instructions: Instruction Description MOV copy byte or word from specified source to specified destination PUSH copy specified word to top of stack POP copy word from top of stack to specified location PUSHA copy all registers to stack POPA copy words from stack to all registers XCHG Exchange bytes or exchange words XLAT translate a byte in AL using a table in memory These are I/O port transfer instructions: Instruction Description IN copy a byte or word from specific port to accumulator OUT copy a byte or word from accumulator to specific port Special address transfer Instructions: Instruction Description LEA load effective address of operand into specified register LDS load DS register and other specified register from memory LES load ES register and other specified register from memory Flag transfer instructions: Instruction Description LAHF load AH with the low byte of flag register SAHF Stores AH register to low byte of flag register PUSHF copy flag register to top of stack POPF copy top of stack word to flag register

X86 INSTRUCTIONS:::DATA TRANSFER INSTRUCTION:::6-LOAD EFFECTIVE ADDRESS

Load Effective Address : Syntax : lea src, dest #GAS Syntax lea dest, src #Intel syntax The lea instruction calculates the address of the src operand and loads it into the dest operand. Operands src Immediate Register Memory dest Register Modified flags No FLAGS are modified by this instruction Load Effective Address calculates its src operand in the same way as the mov instruction does, but rather than loading the contents of that address into the dest operand, it loads the address itself. lea can be used not only for calculating addresses, but also general-purpose unsigned integer arithmetic (with the caveat and possible advantage that FLAGS are unmodified). This can be quite powerful, since the src operand can take up to 4 parameters: base register, index register, scalar multiplier and displacement, e.g. [eax + edx*4 -4] (Intel syntax) or -4(%eax, %edx, 4) (GAS syntax). The scalar multiplier is limited to constant values 1, 2, 4, or 8 for byte, word, double word or quad word offsets respectively. This by itself allows for multiplication of a general register by constant values 2, 3, 4, 5, 8 and 9, as shown below (using NASM syntax): Example : lea ebx, [ebx*2] ; Multiply ebx by 2 lea ebx, [ebx*8+ebx] ; Multiply ebx by 9, which totals ebx*18

X86 INSTRUCTIONS::: DATA TRANSFER INSTRUCTIONS:::5-MOVE STRING

Move byte Syntax : movsb The movsb instruction copies one byte from the memory location specified in esi to the location specified in edi. If the direction flag is cleared, then esi and edi are incremented after the operation. Otherwise, if the direction flag is set, then the pointers are decremented. In that case the copy would happen in the reverse direction, starting at the highest address and moving toward lower addresses until ecx is zero. Operands None. Modified flags No FLAGS are modified by this instruction Example : section .text ; copy mystr into mystr2 mov esi, mystr ; loads address of mystr into esi mov edi, mystr2 ; loads address of mystr2 into edi cld ; clear direction flag (forward) mov ecx,6 rep movsb ; copy six times section .bss mystr2: resb 6 section .data mystr db "Hello", 0x0 Move Word Syntax : movsw The movsw instruction copies one word (two bytes) from the location specified in esi to the location specified in edi. It basically does the same thing as movsb, except with words instead of bytes. Operands None. Modified flags No FLAGS are modified by this instruction Example : section .code ; copy mystr into mystr2 mov esi, mystr mov edi, mystr2 cld mov ecx,4 rep movsw ; mystr2 is now AaBbCca\0 section .bss mystr2: resb 8 section .data mystr db "AaBbCca", 0x0

X86 INSTRUCTIONS::: DATA TRANSFER INSTRUCTION:::4-MOVE SIGN EXTEND

Move sign extend : Syntax : movs src, dest #GAS Syntax movsx dest, src #Intel syntax The movs instruction copies the src operand in the dest operand and pads the remaining bits not provided by src with the sign bit (the MSB) of src. This instruction is useful for copying a signed small value to a bigger register. Operands src Register Memory dest Register Modified flags No FLAGS are modified by this instruction Example : .data byteval: .byte -24 # = 0xe8 .text .global _start _start: movsbw byteval, %ax # %ax is now -24 = 0xffe8 movswl %ax, %ebx # %ebx is now -24 = 0xffffffe8 movsbl byteval, %esi # %esi is now -24 = 0xffffffe8 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS:::DATA TRANSFER INSTRUCTION:::3- MOVE WITH ZERO EXTEND

Move Zero Extend : Syntax : movz src, dest #GAS Syntax movzx dest, src #Intel syntax The movz instruction copies the src operand in the dest operand and pads the remaining bits not provided by src with zeros (0). This instruction is useful for copying a small, unsigned value to a bigger register. Operands arg1 Register Memory arg2 Register Modified flags No FLAGS are modified by this instruction Example : .data byteval: .byte 204 .text .global _start _start: movzbw byteval, %ax # %eax is now 204 movzwl %ax, %ebx # %ebx is now 204 movzbl byteval, %esi # %esi is now 204 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS::::::DATA TRANSFER INSTRUCTION::::2- DATA SWAP

Exchange : Syntax : xchg src, dest #GAS Syntax xchg dest, src #Intel syntax The xchg instruction swaps the src operand with the dest operand. It's like doing three move operations: from dest to a temporary (another register), then from src to dest, then from the temporary to src, except that no register needs to be reserved for temporary storage. If one of the operands is a memory address, then the operation has an implicit LOCK prefix, that is, the exchange operation is atomic. This can have a large performance penalty. It's also worth noting that the common NOP (no op) instruction, 0x90, is the opcode for xchgl %eax, %eax. Operands src Register Memory dest Register Memory However, only one operand can be in memory: the other must be a register. Modified flags No FLAGS are modified by this instruction Example : .data value: .long 2 .text .global _start _start: movl $54, %ebx xorl %eax, %eax xchgl value, %ebx # %ebx is now 2 # value is now 54 xchgw %ax, value # Value is now 0 # %eax is now 54 xchgb %al, %bl # %ebx is now 54 # %eax is now 2 xchgw value(%eax), %ax # value is now 0x00020000 = 131072 # %eax is now 0 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80 Compare and exchange : Syntax : cmpxchg arg2, arg1 #GAS Syntax cmpxchg arg1, arg2 #Intel syntax The cmpxchg instruction has two implicit operands AL/AX/EAX(depending on the size of arg1) and ZF(zero) flag. The instruction compares arg1 to AL/AX/EAX and if they are equal sets arg1 to arg2 and sets the zero flag, otherwise it sets AL/AX/EAX to arg1 and clears the zero flag. Unlike xchg there is not an implicit lock prefix and if the instruction is required to be atomic then lock must be prefixed. Operands arg1 Register Memory arg2 Register Modified flags The ZF flag is modified by this instruction In order to assemble, link and run the program we need to do the following: $ nasm -felf32 -g cmpxchgSpinLock.asm $ gcc -o cmpxchgSpinLock cmpxchgSpinLock.o -lpthread $ ./cmpxchgSpinLock

X86 INSTRUCTIONS:::::DATA TRANSFER INSTRUCTION::::::1- MOVE

Data Transfer Some of the most important and most frequently used instructions are those that move data. Without them, there would be no way for registers or memory to even have anything in them to operate on. Data Transfer Instructions Move Syntax : mov src, dest #GAS Syntax mov dest, src #Intel syntax Move : The mov instruction copies the src operand into the dest operand. Operands src Immediate Register Memory dest Register Memory Modified flags No FLAGS are modified by this instruction Example : .data value: .long 2 .text .global _start _start: movl $6, %eax # %eax is now 6 movw %ax, value # value is now 6 movl $0, %ebx # %ebx is now 0 movb %al, %bl # %ebx is now 6 movl value, %ebx # %ebx is now 6 movl $value, %esi # %esi is now the address of value xorl %ebx, %ebx # %ebx is now 0 movw value(, %ebx, 1), %bx # %ebx is now 6 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS:::::::INTRODUCTION

The different instructions are broken up into groups as follows : Data Transfer Instructions Control Flow Instructions Arithmetic Instructions Logic Instructions Shift and Rotate Instructions Other Instructions x86 Interrupts Conventions The following template will be used for instructions that take no operands: Syntax : Instr The following template will be used for instructions that take 1 operand: Syntax : Instr arg The following template will be used for instructions that take 2 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr src, dest #GAS Syntax Instr dest, src #Intel syntax The following template will be used for instructions that take 3 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr aux, src, dest #GAS Syntax Instr dest, src, aux #Intel syntax Suffixes Some instructions, especially when built for non-Windows platforms (i.e. Unix, Linux, etc.), require the use of suffixes to specify the size of the data which will be the subject of the operation. Some possible suffixes are: b (byte) = 8 bits w (word) = 16 bits l (long) = 32 bits q (quad) = 64 bits Example of the usage with the mov instruction on a 32-bit architecture, GAS syntax: Syntax : # Store the value F into the eax register movl $0x000F, %eax On Intel Syntax you don't have to use the suffix. Based on the register name and the used immediate value the compiler knows which data size to use. Syntax : MOV EAX, 0x000F

GENERAL PURPOSE REGISTERS IN A MICROPROCESSOR

64-bit x86 adds 8 more general-purpose registers, named R8, R9, R10 and so on up to R15. It also introduces a new naming convention that must be used for these new registers and can also be used for the old ones (except that AH, CH, DH and BH have no equivalents). In the new convention : R0 is RAX. R1 is RCX. R2 is RDX. R3 is RBX. R4 is RSP. R5 is RBP. R6 is RSI. R7 is RDI. R8,R9,R10,R11,R12,R13,R14,R15 are the new registers and have no other names. R0D~R15D are the lowermost 32 bits of each register. For example, R0D is EAX. R0W~R15W are the lowermost 16 bits of each register. For example, R0W is AX. R0L~R15L are the lowermost 8 bits of each register. For example, R0L is AL. As well, 64-bit x86 includes SSE2, so each 64-bit x86 CPU has at least 8 registers (named XMM0~XMM7) that are 128 bits wide, but only accessible through SSE instructions. They cannot be used for quadruple-precision (128-bit) floating-point arithmetic, but they can each hold 2 double-precision or 4 single-precision floating-point values for a SIMD parallel instruction. They can also be operated on as 128-bit integers or vectors of shorter integers. If the processor supports AVX, as newer Intel and AMD desktop CPUs do, then each of these registers is actually the lower half of a 256-bit register (named YMM0~YMM7), the whole of which can be accessed with AVX instructions for further parallelization.

ADDRESSING MODE OF THE X86 ARCHITECTURE IN MICROPROCESSOR

The addressing mode indicates the manner in which the operand is presented. Register Addressing (operand address R is in the address field) mov ax, bx ; moves contents of register bx into ax Immediate (actual value is in the field) mov ax, 1 ; moves value of 1 into register ax or mov ax, 010Ch ; moves value of 0x010C into register ax Direct memory addressing (operand address is in the address field) .data my_var dw 0abcdh ; my_var = 0xabcd .code mov ax, [my_var] ; copy my_var content into ax (ax=0xabcd) Direct offset addressing (uses arithmetics to modify address) byte_tbl db 12,15,16,22,..... ; Table of bytes mov al,[byte_tbl+2] mov al,byte_tbl[2] ; same as the former Register Indirect (field points to a register that contains the operand address) mov ax,[di] The registers used for indirect addressing are BX, BP, SI, DI Base-index mov ax,[bx + di] For example, if we are talking about an array, BX contains the address of the beginning of the array, and DI contains the index into the array. Base-index with displacement mov ax,[bx + di + 10]

TWO'S COMPLEMENT REPRESENTING IN MICROPROCESSOR

Two's complement is the standard way of representing negative integers in binary. The sign is changed by inverting all of the bits and adding one. Two's complement example Start: 0001 Invert: 1110 Add One: 1111 0001 represents decimal 1 1111 represents decimal -1

MEMORY OF THE X86 ARCHITECTURE IN A MICROPROCESSOR

The x86 architecture is little-endian, meaning that multi-byte values are written least significant byte first. (This refers only to the ordering of the bytes, not to the bits.) So the 32 bit value B3B2B1B016 on an x86 would be represented in memory as : Little endian representation B0 B1 B2 B3 For example, the 32 bits double word 0x1BA583D4 (the 0x denotes hexadecimal) would be written in memory as : Little endian example D4 83 A5 1B This will be seen as 0xD4 0x83 0xA5 0x1B when doing a memory dump.

INSTRUCTION POINT OF X86 ARCHITECTURE IN MICROPROCESSOR

The EIP register contains the address of the next instruction to be executed if no branching is done. EIP can only be read through the stack after a call instruction.

EFLAGS REGISTERS FOR X86 ARCHITECTURE IN MICROPROCESSOR

The EFLAGS is a 32-bit register used as a collection of bits representing Boolean values to store the results of operations and the state of the processor. The names of these bits are : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 ID VIP VIF AC VM RF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF The bits named 0 and 1 are reserved bits and shouldn't be modified. The different use of these flags are : 0. CF : Carry Flag. Set if the last arithmetic operation carried (addition) or borrowed (subtraction) a bit beyond the size of the register. This is then checked when the operation is followed with an add-with-carry or subtract-with-borrow to deal with values too large for just one register to contain. 2. PF : Parity Flag. Set if the number of set bits in the least significant byte is a multiple of 2. 4. AF : Adjust Flag. Carry of Binary Code Decimal (BCD) numbers arithmetic operations. 6. ZF : Zero Flag. Set if the result of an operation is Zero (0). 7. SF : Sign Flag. Set if the result of an operation is negative. 8. TF : Trap Flag. Set if step by step debugging. 9. IF : Interruption Flag. Set if interrupts are enabled. 10. DF : Direction Flag. Stream direction. If set, string operations will decrement their pointer rather than incrementing it, reading memory backwards. 11. OF : Overflow Flag. Set if signed arithmetic operations result in a value too large for the register to contain. 12-13. IOPL : I/O Privilege Level field (2 bits). I/O Privilege Level of the current process. 14. NT : Nested Task flag. Controls chaining of interrupts. Set if the current process is linked to the next process. 16. RF : Resume Flag. Response to debug exceptions. 17. VM : Virtual-8086 Mode. Set if in 8086 compatibility mode. 18. AC : Alignment Check. Set if alignment checking of memory references is done. 19. VIF : Virtual Interrupt Flag. Virtual image of IF. 20. VIP : Virtual Interrupt Pending flag. Set if an interrupt is pending. 21. ID : Identification Flag. Support for CPUID instruction if can be set.

SEGMENT REGISTERS IN X86 ARCHITECT IN MICROPROCESSOR

The 6 Segment Registers are s : Stack Segment (SS). Pointer to the stack. Code Segment (CS). Pointer to the code. Data Segment (DS). Pointer to the data. Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra'). F Segment (FS). Pointer to more extra data ('F' comes after 'E'). G Segment (GS). Pointer to still more extra data ('G' comes after 'F'). Most applications on most modern operating systems (like FreeBSD, Linux or Microsoft Windows) use a memory model that points nearly all segment registers to the same place (and uses paging instead), effectively disabling their use. Typically the use of FS or GS is an exception to this rule, instead being used to point at thread-specific data

GENERAL PURPOSE RESISTOR IN X86 ARCHITECTURE MICROPROCESSOR

The 8 GPRs are : 1. Accumulator register (AX) :Used in arithmetic operations. 2. Counter register (CX) :Used in shift/rotate instructions and loops. 3. Data register (DX) :Used in arithmetic operations and I/O operations. 4. Base register (BX) :Used as a pointer to data (located in segment register DS, when in segmented mode). 5. Stack Pointer register (SP) :Pointer to the top of the stack. 6. Stack Base Pointer register (BP) :Used to point to the base of the stack. 7. Source Index register (SI) :Used as a pointer to a source in stream operations. 8. Destination Index register (DI): Used as a pointer to a destination in stream operations. The order in which they are listed here is for a reason: it is the same order that is used in a push-to-stack operation. All registers can be accessed in 16-bit and 32-bit modes. In 16-bit mode, the register is identified by its two-letter abbreviation from the list above. In 32-bit mode, this two-letter abbreviation is prefixed with an 'E' (extended). For example, 'EAX' is the accumulator register as a 32-bit value. Similarly, in the 64-bit version, the 'E' is replaced with an 'R', so the 64-bit version of 'EAX' is called 'RAX'. It is also possible to address the first four registers (AX, CX, DX and BX) in their size of 16-bit as two 8-bit halves. The least significant byte (LSB), or low half, is identified by replacing the 'X' with an 'L'. The most significant byte (MSB), or high half, uses an 'H' instead. For example, CL is the LSB of the counter register, whereas CH is its MSB. In total, this gives us five ways to access the accumulator, counter, data and base registers: 64-bit, 32-bit, 16-bit, 8-bit LSB, and 8-bit MSB. The other four are accessed in only three ways: 64-bit, 32-bit and 16-bit. The following table summarises this : Register Accumulator Counter 64-bit RAX RCX 32-bit EAX ECX 16-bit AX CX 8-bit AH AL CH CL Register Data Base 64-bit RDX RBX 32-bit EDX EBX 16-bit DX BX 8-bit DH DL BH BL Register Stack Pointer Stack Base Pointer 64-bit RSP RBP 32-bit ESP EBP 16-bit SP BP 8-bit Register Source Destination 64-bit RSI RDI 32-bit ESI EDI 16-bit SI DI 8-bit

X86 architecture

AMD X86 COMPATIBLE MICROPROCESSOR

Athlon Athlon is the brand name applied to a series of different x86 processors designed and manufactured by AMD. The original Athlon, or Athlon Classic, was the first seventh-generation x86 processor and, in a first, retained the initial performance lead it had over Intel's competing processors for a significant period of time. Turion Turion 64 is the brand name AMD applies to its 64-bit low-power (mobile) processors. Turion 64 processors (but not Turion 64 X2 processors) are compatible with AMD's Socket 754 and are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz HyperTransport bus. Duron The AMD Duron was an x86-compatible computer processor manufactured by AMD. It was released as a low-cost alternative to AMD's own Athlon processor and the Pentium III and Celeron processor lines from rival Intel. Sempron Sempron is, as of 2006, AMD's entry-level desktop CPU, replacing the Duron processor and competing against Intel's Celeron D processor. Opteron The AMD Opteron is the first eighth-generation x86 processor (K8 core), and the first of AMD's AMD64 (x86-64) processors. It is intended to compete in the server market, particularly in the same segment as the Intel Xeon processor.

Intel X86 microprocessor described

8086/8087 (1978) The 8086 was the original x86 microprocessor, with the 8087 as its floating-point coprocessor. The 8086 was Intel's first 16-bit microprocessor with a 20-bit address bus, thus enabling to address up to 1 Megabytes, although there was a limit of 640 Kilobytes of RAM. This limitation is still present in modern CPUs, since they all support the backward-compatible "Real Mode" and boot into it. 8088 (1979) After the development of the 8086, Intel also created the lower-cost 8088. The 8088 was similar to the 8086, but with an 8-bit data bus instead of a 16-bit bus. The address bus was left untouched. 80186/80187 (1982) The 186 was the second Intel chip in the family; the 80187 was its floating point coprocessor. Except for the addition of some new instructions, optimization of some old ones, and an increase in the clock speed, this processor was identical to the 8086. 80286/80287 (1982) The 286 was the third model in the family; the 80287 was its floating point coprocessor. The 286 introduced the “Protected Mode” mode of operation, as opposed to the “Real Mode” that the earlier models used. All subsequent x86 chips can also be made to run in real mode or in protected mode. Switching back from protected mode to real mode was initially not supported, but found to be possible (although relatively slow) by resetting the CPU, then continuing in real mode. 80386 (1985) The 386 was the fourth model in the family. It was the first Intel microprocessor with a 32-bit word. The 386DX model was the original 386 chip, and the 386SX model was an economy model that used the same instruction set, but which only had a 16-bit data bus. Both featured a 32-bits address bus, thus getting rid of the segmented addressing methods used in the previous models and enabling a "flat" memory model, where one register can hold an entire address, instead of relying on two 16-bit registers to create a 20-bit/24-bit address. The flat memory layout was only supported in protected mode. 80486 (1989) The 486 was the fifth model in the family. It had an integrated floating point unit for the first time in x86 history. Early model 80486 DX chips were found to have defective FPUs. They were physically modified to disconnect the FPU portion of the chip and sold as the 486SX (486-SX15, 486-SX20, and 486-SX25). A 487 "math coprocessor" was available to 486SX users and was essentially a 486DX with a working FPU and an extra pin added. Pentium (1993) Intel called it the “Pentium” because they couldn't trademark the code number “80586”. The original Pentium was a faster chip than the 486 with a few other enhancements; later models also integrated the MMX instruction set. Pentium Pro (1995) The Pentium Pro was the sixth-generation architecture microprocessor, originally intended to replace the original Pentium in a full range of applications, but later reduced to a more narrow role as a server and high-end desktop chip. Pentium II (1997) The Pentium II was based on a modified version of the P6 core first used for the Pentium Pro, but with improved 16-bit performance and the addition of the MMX SIMD instruction set, which had already been introduced on the Pentium MMX. Pentium III (1999) Initial versions of the Pentium III were very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions. Pentium 4 (2000) The Pentium 4 had a new 7th generation "NetBurst" architecture. It is currently the fastest x86 chip on the market with respect to clock speed, capable of up to 3.8 GHz. Pentium 4 chips also introduced the notions “Hyper-Threading”, and “Multi-Core” chips. Core (2006) The architecture of the Core processors was actually an even more advanced version of the 6th generation architecture dating back to the 1995 Pentium Pro. The limitations of the NetBurst architecture, especially in mobile applications, were too great to justify creation of more NetBurst processors. The Core processors were designed to operate more efficiently with a lower clock speed. All Core branded processors had two processing cores; the Core Solos had one core disabled, while the Core Duos used both processors. Core 2 (2006) An upgraded, 64-bit version of the Core architecture. All desktop versions are multi-core. i Series (2008) The successor to Core 2 processors featuring Hyper-Threading. Celeron (first model 1998) The Celeron chip is actually a large number of different chip designs, depending on price. Celeron chips are the economy line of chips, and are frequently cheaper than the Pentium chips—even if the Celeron model in question is based off a Pentium architecture. Xeon (first model 1998) The Xeon processors are modern Intel processors made for servers, which have a much larger cache (measured in megabytes in comparison to other chips' kilobyte-sized cache) than the Pentium microprocessors.

X86 family in microprocessor

The term "x86" can refer both to an instruction set architecture and to microprocessors which implement it. The name x86 is derived from the fact that many of Intel's early processors had names ending in "86". The x86 instruction set architecture originated at Intel and has evolved over time by the addition of new instructions as well as the expansion to 64-bits. As of 2009, x86 primarily refers to IA-32 (Intel Architecture, 32-bit) and/or x86-64, the extension to 64-bit computing. Versions of the x86 instruction set architecture have been implemented by Intel, AMD and several other vendors, with each vendor having its own family of x86 processors.

Why learn assembly in a computer programming

Assembly is among some of the oldest tools in a computer-programmer's toolbox. Entire software projects can be written without ever looking at a single line of assembly code. So the question arises : why learn assembly? Assembly language is one of the closest forms of communication that humans can engage in with a computer. With assembly, the programmer can precisely track the flow of data and execution in a program in a mostly human-readable form. Once a program has been compiled, it is difficult (and at times, nearly impossible) to reverse-engineer the code into its original form. As a result, if you wish to examine a program that is already compiled but would rather not stare at hexadecimal or binary, you will need to examine it in assembly language.Since debuggers will frequently only show program code in assembly language. Code written in assembly has less overhead than code written in high-level languages, so assembly code frequently will run much faster than equivalent programs written in other languages. Code that is written in a high-level language can be compiled into assembly and "hand optimized" to squeeze every last bit of speed out of it. Hardware manufacturers such as Intel and AMD add new features and new instructions to their processors, often times the only way to access those features is to use assembly routines. That is, at least until the major compiler vendors add support for those features.