X86 INSTRUCTIONS:::::::INTRODUCTION

The different instructions are broken up into groups as follows : Data Transfer Instructions Control Flow Instructions Arithmetic Instructions Logic Instructions Shift and Rotate Instructions Other Instructions x86 Interrupts Conventions The following template will be used for instructions that take no operands: Syntax : Instr The following template will be used for instructions that take 1 operand: Syntax : Instr arg The following template will be used for instructions that take 2 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr src, dest #GAS Syntax Instr dest, src #Intel syntax The following template will be used for instructions that take 3 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr aux, src, dest #GAS Syntax Instr dest, src, aux #Intel syntax Suffixes Some instructions, especially when built for non-Windows platforms (i.e. Unix, Linux, etc.), require the use of suffixes to specify the size of the data which will be the subject of the operation. Some possible suffixes are: b (byte) = 8 bits w (word) = 16 bits l (long) = 32 bits q (quad) = 64 bits Example of the usage with the mov instruction on a 32-bit architecture, GAS syntax: Syntax : # Store the value F into the eax register movl $0x000F, %eax On Intel Syntax you don't have to use the suffix. Based on the register name and the used immediate value the compiler knows which data size to use. Syntax : MOV EAX, 0x000F

GENERAL PURPOSE REGISTERS IN A MICROPROCESSOR

64-bit x86 adds 8 more general-purpose registers, named R8, R9, R10 and so on up to R15. It also introduces a new naming convention that must be used for these new registers and can also be used for the old ones (except that AH, CH, DH and BH have no equivalents). In the new convention : R0 is RAX. R1 is RCX. R2 is RDX. R3 is RBX. R4 is RSP. R5 is RBP. R6 is RSI. R7 is RDI. R8,R9,R10,R11,R12,R13,R14,R15 are the new registers and have no other names. R0D~R15D are the lowermost 32 bits of each register. For example, R0D is EAX. R0W~R15W are the lowermost 16 bits of each register. For example, R0W is AX. R0L~R15L are the lowermost 8 bits of each register. For example, R0L is AL. As well, 64-bit x86 includes SSE2, so each 64-bit x86 CPU has at least 8 registers (named XMM0~XMM7) that are 128 bits wide, but only accessible through SSE instructions. They cannot be used for quadruple-precision (128-bit) floating-point arithmetic, but they can each hold 2 double-precision or 4 single-precision floating-point values for a SIMD parallel instruction. They can also be operated on as 128-bit integers or vectors of shorter integers. If the processor supports AVX, as newer Intel and AMD desktop CPUs do, then each of these registers is actually the lower half of a 256-bit register (named YMM0~YMM7), the whole of which can be accessed with AVX instructions for further parallelization.

ADDRESSING MODE OF THE X86 ARCHITECTURE IN MICROPROCESSOR

The addressing mode indicates the manner in which the operand is presented. Register Addressing (operand address R is in the address field) mov ax, bx ; moves contents of register bx into ax Immediate (actual value is in the field) mov ax, 1 ; moves value of 1 into register ax or mov ax, 010Ch ; moves value of 0x010C into register ax Direct memory addressing (operand address is in the address field) .data my_var dw 0abcdh ; my_var = 0xabcd .code mov ax, [my_var] ; copy my_var content into ax (ax=0xabcd) Direct offset addressing (uses arithmetics to modify address) byte_tbl db 12,15,16,22,..... ; Table of bytes mov al,[byte_tbl+2] mov al,byte_tbl[2] ; same as the former Register Indirect (field points to a register that contains the operand address) mov ax,[di] The registers used for indirect addressing are BX, BP, SI, DI Base-index mov ax,[bx + di] For example, if we are talking about an array, BX contains the address of the beginning of the array, and DI contains the index into the array. Base-index with displacement mov ax,[bx + di + 10]

TWO'S COMPLEMENT REPRESENTING IN MICROPROCESSOR

Two's complement is the standard way of representing negative integers in binary. The sign is changed by inverting all of the bits and adding one. Two's complement example Start: 0001 Invert: 1110 Add One: 1111 0001 represents decimal 1 1111 represents decimal -1

MEMORY OF THE X86 ARCHITECTURE IN A MICROPROCESSOR

The x86 architecture is little-endian, meaning that multi-byte values are written least significant byte first. (This refers only to the ordering of the bytes, not to the bits.) So the 32 bit value B3B2B1B016 on an x86 would be represented in memory as : Little endian representation B0 B1 B2 B3 For example, the 32 bits double word 0x1BA583D4 (the 0x denotes hexadecimal) would be written in memory as : Little endian example D4 83 A5 1B This will be seen as 0xD4 0x83 0xA5 0x1B when doing a memory dump.

INSTRUCTION POINT OF X86 ARCHITECTURE IN MICROPROCESSOR

The EIP register contains the address of the next instruction to be executed if no branching is done. EIP can only be read through the stack after a call instruction.

EFLAGS REGISTERS FOR X86 ARCHITECTURE IN MICROPROCESSOR

The EFLAGS is a 32-bit register used as a collection of bits representing Boolean values to store the results of operations and the state of the processor. The names of these bits are : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 ID VIP VIF AC VM RF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF The bits named 0 and 1 are reserved bits and shouldn't be modified. The different use of these flags are : 0. CF : Carry Flag. Set if the last arithmetic operation carried (addition) or borrowed (subtraction) a bit beyond the size of the register. This is then checked when the operation is followed with an add-with-carry or subtract-with-borrow to deal with values too large for just one register to contain. 2. PF : Parity Flag. Set if the number of set bits in the least significant byte is a multiple of 2. 4. AF : Adjust Flag. Carry of Binary Code Decimal (BCD) numbers arithmetic operations. 6. ZF : Zero Flag. Set if the result of an operation is Zero (0). 7. SF : Sign Flag. Set if the result of an operation is negative. 8. TF : Trap Flag. Set if step by step debugging. 9. IF : Interruption Flag. Set if interrupts are enabled. 10. DF : Direction Flag. Stream direction. If set, string operations will decrement their pointer rather than incrementing it, reading memory backwards. 11. OF : Overflow Flag. Set if signed arithmetic operations result in a value too large for the register to contain. 12-13. IOPL : I/O Privilege Level field (2 bits). I/O Privilege Level of the current process. 14. NT : Nested Task flag. Controls chaining of interrupts. Set if the current process is linked to the next process. 16. RF : Resume Flag. Response to debug exceptions. 17. VM : Virtual-8086 Mode. Set if in 8086 compatibility mode. 18. AC : Alignment Check. Set if alignment checking of memory references is done. 19. VIF : Virtual Interrupt Flag. Virtual image of IF. 20. VIP : Virtual Interrupt Pending flag. Set if an interrupt is pending. 21. ID : Identification Flag. Support for CPUID instruction if can be set.

SEGMENT REGISTERS IN X86 ARCHITECT IN MICROPROCESSOR

The 6 Segment Registers are s : Stack Segment (SS). Pointer to the stack. Code Segment (CS). Pointer to the code. Data Segment (DS). Pointer to the data. Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra'). F Segment (FS). Pointer to more extra data ('F' comes after 'E'). G Segment (GS). Pointer to still more extra data ('G' comes after 'F'). Most applications on most modern operating systems (like FreeBSD, Linux or Microsoft Windows) use a memory model that points nearly all segment registers to the same place (and uses paging instead), effectively disabling their use. Typically the use of FS or GS is an exception to this rule, instead being used to point at thread-specific data

GENERAL PURPOSE RESISTOR IN X86 ARCHITECTURE MICROPROCESSOR

The 8 GPRs are : 1. Accumulator register (AX) :Used in arithmetic operations. 2. Counter register (CX) :Used in shift/rotate instructions and loops. 3. Data register (DX) :Used in arithmetic operations and I/O operations. 4. Base register (BX) :Used as a pointer to data (located in segment register DS, when in segmented mode). 5. Stack Pointer register (SP) :Pointer to the top of the stack. 6. Stack Base Pointer register (BP) :Used to point to the base of the stack. 7. Source Index register (SI) :Used as a pointer to a source in stream operations. 8. Destination Index register (DI): Used as a pointer to a destination in stream operations. The order in which they are listed here is for a reason: it is the same order that is used in a push-to-stack operation. All registers can be accessed in 16-bit and 32-bit modes. In 16-bit mode, the register is identified by its two-letter abbreviation from the list above. In 32-bit mode, this two-letter abbreviation is prefixed with an 'E' (extended). For example, 'EAX' is the accumulator register as a 32-bit value. Similarly, in the 64-bit version, the 'E' is replaced with an 'R', so the 64-bit version of 'EAX' is called 'RAX'. It is also possible to address the first four registers (AX, CX, DX and BX) in their size of 16-bit as two 8-bit halves. The least significant byte (LSB), or low half, is identified by replacing the 'X' with an 'L'. The most significant byte (MSB), or high half, uses an 'H' instead. For example, CL is the LSB of the counter register, whereas CH is its MSB. In total, this gives us five ways to access the accumulator, counter, data and base registers: 64-bit, 32-bit, 16-bit, 8-bit LSB, and 8-bit MSB. The other four are accessed in only three ways: 64-bit, 32-bit and 16-bit. The following table summarises this : Register Accumulator Counter 64-bit RAX RCX 32-bit EAX ECX 16-bit AX CX 8-bit AH AL CH CL Register Data Base 64-bit RDX RBX 32-bit EDX EBX 16-bit DX BX 8-bit DH DL BH BL Register Stack Pointer Stack Base Pointer 64-bit RSP RBP 32-bit ESP EBP 16-bit SP BP 8-bit Register Source Destination 64-bit RSI RDI 32-bit ESI EDI 16-bit SI DI 8-bit

X86 architecture

AMD X86 COMPATIBLE MICROPROCESSOR

Athlon Athlon is the brand name applied to a series of different x86 processors designed and manufactured by AMD. The original Athlon, or Athlon Classic, was the first seventh-generation x86 processor and, in a first, retained the initial performance lead it had over Intel's competing processors for a significant period of time. Turion Turion 64 is the brand name AMD applies to its 64-bit low-power (mobile) processors. Turion 64 processors (but not Turion 64 X2 processors) are compatible with AMD's Socket 754 and are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz HyperTransport bus. Duron The AMD Duron was an x86-compatible computer processor manufactured by AMD. It was released as a low-cost alternative to AMD's own Athlon processor and the Pentium III and Celeron processor lines from rival Intel. Sempron Sempron is, as of 2006, AMD's entry-level desktop CPU, replacing the Duron processor and competing against Intel's Celeron D processor. Opteron The AMD Opteron is the first eighth-generation x86 processor (K8 core), and the first of AMD's AMD64 (x86-64) processors. It is intended to compete in the server market, particularly in the same segment as the Intel Xeon processor.

Intel X86 microprocessor described

8086/8087 (1978) The 8086 was the original x86 microprocessor, with the 8087 as its floating-point coprocessor. The 8086 was Intel's first 16-bit microprocessor with a 20-bit address bus, thus enabling to address up to 1 Megabytes, although there was a limit of 640 Kilobytes of RAM. This limitation is still present in modern CPUs, since they all support the backward-compatible "Real Mode" and boot into it. 8088 (1979) After the development of the 8086, Intel also created the lower-cost 8088. The 8088 was similar to the 8086, but with an 8-bit data bus instead of a 16-bit bus. The address bus was left untouched. 80186/80187 (1982) The 186 was the second Intel chip in the family; the 80187 was its floating point coprocessor. Except for the addition of some new instructions, optimization of some old ones, and an increase in the clock speed, this processor was identical to the 8086. 80286/80287 (1982) The 286 was the third model in the family; the 80287 was its floating point coprocessor. The 286 introduced the “Protected Mode” mode of operation, as opposed to the “Real Mode” that the earlier models used. All subsequent x86 chips can also be made to run in real mode or in protected mode. Switching back from protected mode to real mode was initially not supported, but found to be possible (although relatively slow) by resetting the CPU, then continuing in real mode. 80386 (1985) The 386 was the fourth model in the family. It was the first Intel microprocessor with a 32-bit word. The 386DX model was the original 386 chip, and the 386SX model was an economy model that used the same instruction set, but which only had a 16-bit data bus. Both featured a 32-bits address bus, thus getting rid of the segmented addressing methods used in the previous models and enabling a "flat" memory model, where one register can hold an entire address, instead of relying on two 16-bit registers to create a 20-bit/24-bit address. The flat memory layout was only supported in protected mode. 80486 (1989) The 486 was the fifth model in the family. It had an integrated floating point unit for the first time in x86 history. Early model 80486 DX chips were found to have defective FPUs. They were physically modified to disconnect the FPU portion of the chip and sold as the 486SX (486-SX15, 486-SX20, and 486-SX25). A 487 "math coprocessor" was available to 486SX users and was essentially a 486DX with a working FPU and an extra pin added. Pentium (1993) Intel called it the “Pentium” because they couldn't trademark the code number “80586”. The original Pentium was a faster chip than the 486 with a few other enhancements; later models also integrated the MMX instruction set. Pentium Pro (1995) The Pentium Pro was the sixth-generation architecture microprocessor, originally intended to replace the original Pentium in a full range of applications, but later reduced to a more narrow role as a server and high-end desktop chip. Pentium II (1997) The Pentium II was based on a modified version of the P6 core first used for the Pentium Pro, but with improved 16-bit performance and the addition of the MMX SIMD instruction set, which had already been introduced on the Pentium MMX. Pentium III (1999) Initial versions of the Pentium III were very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions. Pentium 4 (2000) The Pentium 4 had a new 7th generation "NetBurst" architecture. It is currently the fastest x86 chip on the market with respect to clock speed, capable of up to 3.8 GHz. Pentium 4 chips also introduced the notions “Hyper-Threading”, and “Multi-Core” chips. Core (2006) The architecture of the Core processors was actually an even more advanced version of the 6th generation architecture dating back to the 1995 Pentium Pro. The limitations of the NetBurst architecture, especially in mobile applications, were too great to justify creation of more NetBurst processors. The Core processors were designed to operate more efficiently with a lower clock speed. All Core branded processors had two processing cores; the Core Solos had one core disabled, while the Core Duos used both processors. Core 2 (2006) An upgraded, 64-bit version of the Core architecture. All desktop versions are multi-core. i Series (2008) The successor to Core 2 processors featuring Hyper-Threading. Celeron (first model 1998) The Celeron chip is actually a large number of different chip designs, depending on price. Celeron chips are the economy line of chips, and are frequently cheaper than the Pentium chips—even if the Celeron model in question is based off a Pentium architecture. Xeon (first model 1998) The Xeon processors are modern Intel processors made for servers, which have a much larger cache (measured in megabytes in comparison to other chips' kilobyte-sized cache) than the Pentium microprocessors.

X86 family in microprocessor

The term "x86" can refer both to an instruction set architecture and to microprocessors which implement it. The name x86 is derived from the fact that many of Intel's early processors had names ending in "86". The x86 instruction set architecture originated at Intel and has evolved over time by the addition of new instructions as well as the expansion to 64-bits. As of 2009, x86 primarily refers to IA-32 (Intel Architecture, 32-bit) and/or x86-64, the extension to 64-bit computing. Versions of the x86 instruction set architecture have been implemented by Intel, AMD and several other vendors, with each vendor having its own family of x86 processors.

Why learn assembly in a computer programming

Assembly is among some of the oldest tools in a computer-programmer's toolbox. Entire software projects can be written without ever looking at a single line of assembly code. So the question arises : why learn assembly? Assembly language is one of the closest forms of communication that humans can engage in with a computer. With assembly, the programmer can precisely track the flow of data and execution in a program in a mostly human-readable form. Once a program has been compiled, it is difficult (and at times, nearly impossible) to reverse-engineer the code into its original form. As a result, if you wish to examine a program that is already compiled but would rather not stare at hexadecimal or binary, you will need to examine it in assembly language.Since debuggers will frequently only show program code in assembly language. Code written in assembly has less overhead than code written in high-level languages, so assembly code frequently will run much faster than equivalent programs written in other languages. Code that is written in a high-level language can be compiled into assembly and "hand optimized" to squeeze every last bit of speed out of it. Hardware manufacturers such as Intel and AMD add new features and new instructions to their processors, often times the only way to access those features is to use assembly routines. That is, at least until the major compiler vendors add support for those features.

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