DATA TRANSFER INSTRUCTION FOR 8086 MICROPROCESSOR

General purpose byte or word transfer instructions: Instruction Description MOV copy byte or word from specified source to specified destination PUSH copy specified word to top of stack POP copy word from top of stack to specified location PUSHA copy all registers to stack POPA copy words from stack to all registers XCHG Exchange bytes or exchange words XLAT translate a byte in AL using a table in memory These are I/O port transfer instructions: Instruction Description IN copy a byte or word from specific port to accumulator OUT copy a byte or word from accumulator to specific port Special address transfer Instructions: Instruction Description LEA load effective address of operand into specified register LDS load DS register and other specified register from memory LES load ES register and other specified register from memory Flag transfer instructions: Instruction Description LAHF load AH with the low byte of flag register SAHF Stores AH register to low byte of flag register PUSHF copy flag register to top of stack POPF copy top of stack word to flag register

X86 INSTRUCTIONS:::DATA TRANSFER INSTRUCTION:::6-LOAD EFFECTIVE ADDRESS

Load Effective Address : Syntax : lea src, dest #GAS Syntax lea dest, src #Intel syntax The lea instruction calculates the address of the src operand and loads it into the dest operand. Operands src Immediate Register Memory dest Register Modified flags No FLAGS are modified by this instruction Load Effective Address calculates its src operand in the same way as the mov instruction does, but rather than loading the contents of that address into the dest operand, it loads the address itself. lea can be used not only for calculating addresses, but also general-purpose unsigned integer arithmetic (with the caveat and possible advantage that FLAGS are unmodified). This can be quite powerful, since the src operand can take up to 4 parameters: base register, index register, scalar multiplier and displacement, e.g. [eax + edx*4 -4] (Intel syntax) or -4(%eax, %edx, 4) (GAS syntax). The scalar multiplier is limited to constant values 1, 2, 4, or 8 for byte, word, double word or quad word offsets respectively. This by itself allows for multiplication of a general register by constant values 2, 3, 4, 5, 8 and 9, as shown below (using NASM syntax): Example : lea ebx, [ebx*2] ; Multiply ebx by 2 lea ebx, [ebx*8+ebx] ; Multiply ebx by 9, which totals ebx*18

X86 INSTRUCTIONS::: DATA TRANSFER INSTRUCTIONS:::5-MOVE STRING

Move byte Syntax : movsb The movsb instruction copies one byte from the memory location specified in esi to the location specified in edi. If the direction flag is cleared, then esi and edi are incremented after the operation. Otherwise, if the direction flag is set, then the pointers are decremented. In that case the copy would happen in the reverse direction, starting at the highest address and moving toward lower addresses until ecx is zero. Operands None. Modified flags No FLAGS are modified by this instruction Example : section .text ; copy mystr into mystr2 mov esi, mystr ; loads address of mystr into esi mov edi, mystr2 ; loads address of mystr2 into edi cld ; clear direction flag (forward) mov ecx,6 rep movsb ; copy six times section .bss mystr2: resb 6 section .data mystr db "Hello", 0x0 Move Word Syntax : movsw The movsw instruction copies one word (two bytes) from the location specified in esi to the location specified in edi. It basically does the same thing as movsb, except with words instead of bytes. Operands None. Modified flags No FLAGS are modified by this instruction Example : section .code ; copy mystr into mystr2 mov esi, mystr mov edi, mystr2 cld mov ecx,4 rep movsw ; mystr2 is now AaBbCca\0 section .bss mystr2: resb 8 section .data mystr db "AaBbCca", 0x0

X86 INSTRUCTIONS::: DATA TRANSFER INSTRUCTION:::4-MOVE SIGN EXTEND

Move sign extend : Syntax : movs src, dest #GAS Syntax movsx dest, src #Intel syntax The movs instruction copies the src operand in the dest operand and pads the remaining bits not provided by src with the sign bit (the MSB) of src. This instruction is useful for copying a signed small value to a bigger register. Operands src Register Memory dest Register Modified flags No FLAGS are modified by this instruction Example : .data byteval: .byte -24 # = 0xe8 .text .global _start _start: movsbw byteval, %ax # %ax is now -24 = 0xffe8 movswl %ax, %ebx # %ebx is now -24 = 0xffffffe8 movsbl byteval, %esi # %esi is now -24 = 0xffffffe8 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS:::DATA TRANSFER INSTRUCTION:::3- MOVE WITH ZERO EXTEND

Move Zero Extend : Syntax : movz src, dest #GAS Syntax movzx dest, src #Intel syntax The movz instruction copies the src operand in the dest operand and pads the remaining bits not provided by src with zeros (0). This instruction is useful for copying a small, unsigned value to a bigger register. Operands arg1 Register Memory arg2 Register Modified flags No FLAGS are modified by this instruction Example : .data byteval: .byte 204 .text .global _start _start: movzbw byteval, %ax # %eax is now 204 movzwl %ax, %ebx # %ebx is now 204 movzbl byteval, %esi # %esi is now 204 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS::::::DATA TRANSFER INSTRUCTION::::2- DATA SWAP

Exchange : Syntax : xchg src, dest #GAS Syntax xchg dest, src #Intel syntax The xchg instruction swaps the src operand with the dest operand. It's like doing three move operations: from dest to a temporary (another register), then from src to dest, then from the temporary to src, except that no register needs to be reserved for temporary storage. If one of the operands is a memory address, then the operation has an implicit LOCK prefix, that is, the exchange operation is atomic. This can have a large performance penalty. It's also worth noting that the common NOP (no op) instruction, 0x90, is the opcode for xchgl %eax, %eax. Operands src Register Memory dest Register Memory However, only one operand can be in memory: the other must be a register. Modified flags No FLAGS are modified by this instruction Example : .data value: .long 2 .text .global _start _start: movl $54, %ebx xorl %eax, %eax xchgl value, %ebx # %ebx is now 2 # value is now 54 xchgw %ax, value # Value is now 0 # %eax is now 54 xchgb %al, %bl # %ebx is now 54 # %eax is now 2 xchgw value(%eax), %ax # value is now 0x00020000 = 131072 # %eax is now 0 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80 Compare and exchange : Syntax : cmpxchg arg2, arg1 #GAS Syntax cmpxchg arg1, arg2 #Intel syntax The cmpxchg instruction has two implicit operands AL/AX/EAX(depending on the size of arg1) and ZF(zero) flag. The instruction compares arg1 to AL/AX/EAX and if they are equal sets arg1 to arg2 and sets the zero flag, otherwise it sets AL/AX/EAX to arg1 and clears the zero flag. Unlike xchg there is not an implicit lock prefix and if the instruction is required to be atomic then lock must be prefixed. Operands arg1 Register Memory arg2 Register Modified flags The ZF flag is modified by this instruction In order to assemble, link and run the program we need to do the following: $ nasm -felf32 -g cmpxchgSpinLock.asm $ gcc -o cmpxchgSpinLock cmpxchgSpinLock.o -lpthread $ ./cmpxchgSpinLock

X86 INSTRUCTIONS:::::DATA TRANSFER INSTRUCTION::::::1- MOVE

Data Transfer Some of the most important and most frequently used instructions are those that move data. Without them, there would be no way for registers or memory to even have anything in them to operate on. Data Transfer Instructions Move Syntax : mov src, dest #GAS Syntax mov dest, src #Intel syntax Move : The mov instruction copies the src operand into the dest operand. Operands src Immediate Register Memory dest Register Memory Modified flags No FLAGS are modified by this instruction Example : .data value: .long 2 .text .global _start _start: movl $6, %eax # %eax is now 6 movw %ax, value # value is now 6 movl $0, %ebx # %ebx is now 0 movb %al, %bl # %ebx is now 6 movl value, %ebx # %ebx is now 6 movl $value, %esi # %esi is now the address of value xorl %ebx, %ebx # %ebx is now 0 movw value(, %ebx, 1), %bx # %ebx is now 6 # Linux sys_exit mov $1, %eax xorl %ebx, %ebx int $0x80

X86 INSTRUCTIONS:::::::INTRODUCTION

The different instructions are broken up into groups as follows : Data Transfer Instructions Control Flow Instructions Arithmetic Instructions Logic Instructions Shift and Rotate Instructions Other Instructions x86 Interrupts Conventions The following template will be used for instructions that take no operands: Syntax : Instr The following template will be used for instructions that take 1 operand: Syntax : Instr arg The following template will be used for instructions that take 2 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr src, dest #GAS Syntax Instr dest, src #Intel syntax The following template will be used for instructions that take 3 operands. Notice how the format of the instruction is different for different assemblers. Syntax : Instr aux, src, dest #GAS Syntax Instr dest, src, aux #Intel syntax Suffixes Some instructions, especially when built for non-Windows platforms (i.e. Unix, Linux, etc.), require the use of suffixes to specify the size of the data which will be the subject of the operation. Some possible suffixes are: b (byte) = 8 bits w (word) = 16 bits l (long) = 32 bits q (quad) = 64 bits Example of the usage with the mov instruction on a 32-bit architecture, GAS syntax: Syntax : # Store the value F into the eax register movl $0x000F, %eax On Intel Syntax you don't have to use the suffix. Based on the register name and the used immediate value the compiler knows which data size to use. Syntax : MOV EAX, 0x000F

GENERAL PURPOSE REGISTERS IN A MICROPROCESSOR

64-bit x86 adds 8 more general-purpose registers, named R8, R9, R10 and so on up to R15. It also introduces a new naming convention that must be used for these new registers and can also be used for the old ones (except that AH, CH, DH and BH have no equivalents). In the new convention : R0 is RAX. R1 is RCX. R2 is RDX. R3 is RBX. R4 is RSP. R5 is RBP. R6 is RSI. R7 is RDI. R8,R9,R10,R11,R12,R13,R14,R15 are the new registers and have no other names. R0D~R15D are the lowermost 32 bits of each register. For example, R0D is EAX. R0W~R15W are the lowermost 16 bits of each register. For example, R0W is AX. R0L~R15L are the lowermost 8 bits of each register. For example, R0L is AL. As well, 64-bit x86 includes SSE2, so each 64-bit x86 CPU has at least 8 registers (named XMM0~XMM7) that are 128 bits wide, but only accessible through SSE instructions. They cannot be used for quadruple-precision (128-bit) floating-point arithmetic, but they can each hold 2 double-precision or 4 single-precision floating-point values for a SIMD parallel instruction. They can also be operated on as 128-bit integers or vectors of shorter integers. If the processor supports AVX, as newer Intel and AMD desktop CPUs do, then each of these registers is actually the lower half of a 256-bit register (named YMM0~YMM7), the whole of which can be accessed with AVX instructions for further parallelization.

ADDRESSING MODE OF THE X86 ARCHITECTURE IN MICROPROCESSOR

The addressing mode indicates the manner in which the operand is presented. Register Addressing (operand address R is in the address field) mov ax, bx ; moves contents of register bx into ax Immediate (actual value is in the field) mov ax, 1 ; moves value of 1 into register ax or mov ax, 010Ch ; moves value of 0x010C into register ax Direct memory addressing (operand address is in the address field) .data my_var dw 0abcdh ; my_var = 0xabcd .code mov ax, [my_var] ; copy my_var content into ax (ax=0xabcd) Direct offset addressing (uses arithmetics to modify address) byte_tbl db 12,15,16,22,..... ; Table of bytes mov al,[byte_tbl+2] mov al,byte_tbl[2] ; same as the former Register Indirect (field points to a register that contains the operand address) mov ax,[di] The registers used for indirect addressing are BX, BP, SI, DI Base-index mov ax,[bx + di] For example, if we are talking about an array, BX contains the address of the beginning of the array, and DI contains the index into the array. Base-index with displacement mov ax,[bx + di + 10]

TWO'S COMPLEMENT REPRESENTING IN MICROPROCESSOR

Two's complement is the standard way of representing negative integers in binary. The sign is changed by inverting all of the bits and adding one. Two's complement example Start: 0001 Invert: 1110 Add One: 1111 0001 represents decimal 1 1111 represents decimal -1

MEMORY OF THE X86 ARCHITECTURE IN A MICROPROCESSOR

The x86 architecture is little-endian, meaning that multi-byte values are written least significant byte first. (This refers only to the ordering of the bytes, not to the bits.) So the 32 bit value B3B2B1B016 on an x86 would be represented in memory as : Little endian representation B0 B1 B2 B3 For example, the 32 bits double word 0x1BA583D4 (the 0x denotes hexadecimal) would be written in memory as : Little endian example D4 83 A5 1B This will be seen as 0xD4 0x83 0xA5 0x1B when doing a memory dump.

INSTRUCTION POINT OF X86 ARCHITECTURE IN MICROPROCESSOR

The EIP register contains the address of the next instruction to be executed if no branching is done. EIP can only be read through the stack after a call instruction.

EFLAGS REGISTERS FOR X86 ARCHITECTURE IN MICROPROCESSOR

The EFLAGS is a 32-bit register used as a collection of bits representing Boolean values to store the results of operations and the state of the processor. The names of these bits are : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 ID VIP VIF AC VM RF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF The bits named 0 and 1 are reserved bits and shouldn't be modified. The different use of these flags are : 0. CF : Carry Flag. Set if the last arithmetic operation carried (addition) or borrowed (subtraction) a bit beyond the size of the register. This is then checked when the operation is followed with an add-with-carry or subtract-with-borrow to deal with values too large for just one register to contain. 2. PF : Parity Flag. Set if the number of set bits in the least significant byte is a multiple of 2. 4. AF : Adjust Flag. Carry of Binary Code Decimal (BCD) numbers arithmetic operations. 6. ZF : Zero Flag. Set if the result of an operation is Zero (0). 7. SF : Sign Flag. Set if the result of an operation is negative. 8. TF : Trap Flag. Set if step by step debugging. 9. IF : Interruption Flag. Set if interrupts are enabled. 10. DF : Direction Flag. Stream direction. If set, string operations will decrement their pointer rather than incrementing it, reading memory backwards. 11. OF : Overflow Flag. Set if signed arithmetic operations result in a value too large for the register to contain. 12-13. IOPL : I/O Privilege Level field (2 bits). I/O Privilege Level of the current process. 14. NT : Nested Task flag. Controls chaining of interrupts. Set if the current process is linked to the next process. 16. RF : Resume Flag. Response to debug exceptions. 17. VM : Virtual-8086 Mode. Set if in 8086 compatibility mode. 18. AC : Alignment Check. Set if alignment checking of memory references is done. 19. VIF : Virtual Interrupt Flag. Virtual image of IF. 20. VIP : Virtual Interrupt Pending flag. Set if an interrupt is pending. 21. ID : Identification Flag. Support for CPUID instruction if can be set.

SEGMENT REGISTERS IN X86 ARCHITECT IN MICROPROCESSOR

The 6 Segment Registers are s : Stack Segment (SS). Pointer to the stack. Code Segment (CS). Pointer to the code. Data Segment (DS). Pointer to the data. Extra Segment (ES). Pointer to extra data ('E' stands for 'Extra'). F Segment (FS). Pointer to more extra data ('F' comes after 'E'). G Segment (GS). Pointer to still more extra data ('G' comes after 'F'). Most applications on most modern operating systems (like FreeBSD, Linux or Microsoft Windows) use a memory model that points nearly all segment registers to the same place (and uses paging instead), effectively disabling their use. Typically the use of FS or GS is an exception to this rule, instead being used to point at thread-specific data

GENERAL PURPOSE RESISTOR IN X86 ARCHITECTURE MICROPROCESSOR

The 8 GPRs are : 1. Accumulator register (AX) :Used in arithmetic operations. 2. Counter register (CX) :Used in shift/rotate instructions and loops. 3. Data register (DX) :Used in arithmetic operations and I/O operations. 4. Base register (BX) :Used as a pointer to data (located in segment register DS, when in segmented mode). 5. Stack Pointer register (SP) :Pointer to the top of the stack. 6. Stack Base Pointer register (BP) :Used to point to the base of the stack. 7. Source Index register (SI) :Used as a pointer to a source in stream operations. 8. Destination Index register (DI): Used as a pointer to a destination in stream operations. The order in which they are listed here is for a reason: it is the same order that is used in a push-to-stack operation. All registers can be accessed in 16-bit and 32-bit modes. In 16-bit mode, the register is identified by its two-letter abbreviation from the list above. In 32-bit mode, this two-letter abbreviation is prefixed with an 'E' (extended). For example, 'EAX' is the accumulator register as a 32-bit value. Similarly, in the 64-bit version, the 'E' is replaced with an 'R', so the 64-bit version of 'EAX' is called 'RAX'. It is also possible to address the first four registers (AX, CX, DX and BX) in their size of 16-bit as two 8-bit halves. The least significant byte (LSB), or low half, is identified by replacing the 'X' with an 'L'. The most significant byte (MSB), or high half, uses an 'H' instead. For example, CL is the LSB of the counter register, whereas CH is its MSB. In total, this gives us five ways to access the accumulator, counter, data and base registers: 64-bit, 32-bit, 16-bit, 8-bit LSB, and 8-bit MSB. The other four are accessed in only three ways: 64-bit, 32-bit and 16-bit. The following table summarises this : Register Accumulator Counter 64-bit RAX RCX 32-bit EAX ECX 16-bit AX CX 8-bit AH AL CH CL Register Data Base 64-bit RDX RBX 32-bit EDX EBX 16-bit DX BX 8-bit DH DL BH BL Register Stack Pointer Stack Base Pointer 64-bit RSP RBP 32-bit ESP EBP 16-bit SP BP 8-bit Register Source Destination 64-bit RSI RDI 32-bit ESI EDI 16-bit SI DI 8-bit

X86 architecture